Fabrication of integrated circuitry typically involves forming electrical connections to substrate node locations. In the context of integrated circuit memory devices, such as dynamic random access memory devices, such electrical connections include those which are made to and between storage capacitors and substrate diffusion regions.
In the past, there have been at least two ways to make such electrical connections. A first way of forming such electrical connections involves depositing a thick insulator material, such as borophosphosilicate glass, over the substrate and then conducting a self-aligned etch thereof to form a contact opening. The contact opening, or at least a portion thereof, is subsequently filled with conductive material. As aspect ratios of such contact openings increase, it becomes more challenging to form such openings and electrical connections. A second way of forming such electrical connections involves depositing a conductive material over the entire substrate, patterning and etching such material to define desired electrical connections, and subsequently forming an insulating dielectric layer over the substrate. Contact openings can then be etched through the dielectric layer. Again, challenges are posed with respect to etching the contact openings through the dielectric layer.
This invention grew out of concerns associated with improving the manner in which electrical connections are made to or with integrated circuit substrate node locations. This invention also grew out of concerns associated with improving the manner in which electrical connections are made with integrated circuit memory cell node locations.